Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory, among others.
Flash memory devices are utilized as non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption.
Uses for flash memory include memory for personal computers such as a portable memory stick and a solid state drive (SSD), personal digital assistants (PDAs), digital cameras, and cellular telephones, portable music players (e.g., MP3 players), and movie players, among others. Program code and system data, such as a basic input/output system (BIOS), are typically stored in flash memory devices. This information can be used in personal computer systems, and other electronic devices.
Two common types of flash memory array architectures are the “NAND” and “NOR” architectures, so called for the logical form in which the basic memory cell configuration of each is arranged. The floating gate memory cells of the memory array are typically arranged in a matrix. The gates of each floating gate memory cell in a “row” of the array are coupled to an access line (one example which is a “word line”). In a NOR architecture, the drains of each memory cell in a “column” of the array are coupled to a data line (one example which is a “bit line”). In a NAND architecture, the drain of individual memory cells is not directly coupled to a bit line. Instead, the memory cells of the array are coupled together in series, source to drain, between a source line and a bit line.
The NOR architecture floating gate memory array is accessed through a row decoder activating a row of floating gate memory cells by selecting the word line coupled to their gates. The row of selected memory cells then place their data values on the bit lines by causing different currents to flow depending on the state to which a particular cell is programmed.
The NAND architecture memory array is also accessed through a row decoder activating a row of memory cells by selecting the word line coupled to their gates. A high bias voltage is applied to a select gate drain line SG(D). In addition, the word lines coupled to the gates of the unselected memory cells of each group are driven (e.g., at Vpass) to operate the unselected memory cells of each group as pass transistors so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series coupled group, restricted only by the selected memory cells of each group. This places the current encoded data values of the row of selected memory cells on the bit lines.
Memory cells can be programmed to an intended state. That is, electric charge can be placed on or removed from the floating gate of a memory cell to put the cell into a number of programmed states. For example, a single level cell (SLC) can represent one of two programmed states (e.g., 1 or 0). The memory cell is commonly referred to as being “erased” when representing the programmed state corresponding to charge being removed from the floating gate.
Flash memory cells can also represent one of more than two programmed states, such as to represent more than two binary digits (e.g. 1111, 0111, 0011, 1011, 1001, 0001, 0101, 1101, 1100, 0100, 0000, 1000, 1010, 0010, 0110, and 1110). Such cells may be referred to as multi state memory cells, multi-digit cells, or multilevel cells (MLCs). MLCs can allow the manufacture of higher density memories without increasing the number of memory cells since each cell can represent more than one binary digit (e.g., more than one bit). MLCs can, in some embodiments, each represent one of more than two programmed states (e.g., a cell capable of representing four digits can be put into sixteen programmed states). For some MLCs, one of the sixteen programmed states can be an erased state, while the other states are programmed states.